The present invention relates to generally semiconductor devices, and more specifically, to the fabrication of fin-type semiconductor devices.
As the desire to reduce semiconductor scaling continues, planar-type semiconductor devices have been replaced with fin-type semiconductor devices, which are typically referred to as fin-type field effect transistor devices, or “finFETs.” Recent studies have shown that the implementation of high-k gate dielectrics in the gate stack surrounding the channel region can further contribute to the scale reduction of finFET devices.
Hafnium-based materials such as hafnium oxide (HfO2) and hafnium silicate oxynitride (HfSixOyNz), for example, are considered the most promising high-k gate dielectric candidates because of their high thermodynamic stability, high permittivity, wide bandgap, and large band offset with respect to conventional channel materials. However, the presence of high-k layers and changes in thickness in the channel region has a significant impact on the electrical characteristics of the finFET device. For instance, high-k materials are susceptible to fabrication processing damage and/or high-k layer crystallization near the gate edge which can result in trapping and de-trapping of carriers. These traps have energies close to the silicon conduction-band edge, and therefore can introduce undesirable noise, typically referred to as flicker noise, in the channel region. The noise magnitude (i.e., 1/f) and the effective oxide trap density in finFETs implementing high-k dielectric transistors can generate noise magnitudes reaching one to two orders higher than those in SiO2 and SiON devices. The thickness of the interfacial layer also has a key role in the susceptibility of carrier trappings, and thus the overall noise levels.